Shallow trench isolation (STI) is being widely used for isolation in large-scale integrated circuits (ICs) to isolate the active areas of transistors and other devices from each other. STI is formed prior to transistor formation. Typically, a pad oxide and pad nitride are deposited over the surface. The pad oxide and nitride are then patterned and etched to form a hard mask for the trench etch. A shallow trench is then etched into the semiconductor surface. A trench liner is then formed on the surface of the trench and the trench is filled with a dielectric material, such as silicon dioxide. This is followed by CMP and removal of nitride to create active areas.
As ICs become denser, both the active areas and the trench shrink. This places increasing demands on the lithography used to pattern the hard mask/trench. It also requires tighter control of the trench etch. The STI lithography and etch can be monitored/evaluated using top-view SEM (scanning-electron-microscope)/cross-sectional SEM. Since large amounts of data are required for wafer uniformity, SEM analysis becomes time-consuming. Accordingly, a method for monitoring/developing/evaluating STI lithography and etch that is less time consuming and provides wafer uniformity information is desired.